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refactor clock

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JSL : RTL to JML
SEC not necessary if we branch on BEQ, since BEQ implies a set carry
made carry_bit a sublabel
This commit is contained in:
spannerisms
2021-03-24 07:42:34 -04:00
parent ffd1db722b
commit 97e3a995e0
1 changed files with 7 additions and 9 deletions
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16
clock.asm
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@@ -66,8 +66,7 @@ endmacro
Clock_Test:
JSL.l Clock_Init
JSL.l Clock_IsSupported
RTL
JML.l Clock_IsSupported
;--------------------------------------------------------------------------------
; Clock_Init
@@ -112,11 +111,10 @@ Clock_IsSupported:
PHA : PHX
LDX #$00;
-
LDA $002800 : AND.b #$0F : CMP #$0F : BEQ + ; check for clock chip ready signal
CPX.b #$0E : !BLT ++ : CLC : BRA .done : ++ ; if we've read 14 bytes with no success, unset carry and exit
INX
BRA - : +
SEC ; found a clock chip
LDA $002800 : AND.b #$0F : CMP #$0F : BEQ .done ; check for clock chip ready signal
CPX.b #$0E : BCC ++ : CLC : BRA .done ; if we've read 14 bytes with no success, unset carry and exit
++ INX
BRA -
.done
PLX : PLA
RTL
@@ -197,9 +195,9 @@ Multiply_A16Y8:
CLC
ADC $4216
LDY $4217
BCC carry_bit
BCC .carry_bit
INY
carry_bit:
.carry_bit:
XBA
REP #$20 ; set 16-bit accumulator
RTL