Removed rails using a dynamic flag
This commit is contained in:
aerinon
136
roomloading.asm
136
roomloading.asm
@@ -15,9 +15,6 @@ LoadRoomHook:
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dl IcePalaceBombosNE ; 03
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dl CastleEastEntrance ; 04
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dl CastleWestEntrance ; 05
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dl PoDFallingBridge ; 06
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dl PoDArena ; 07
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dl MireBKPond ; 08
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NoCallback:
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RTL
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@@ -92,138 +89,11 @@ CastleEastEntrance: ; new solution (see Rain Prevention)
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CastleWestEntrance: ; new solution (see Rain Prevention)
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RTL
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PoDFallingBridge:
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LDA.l DRFlags : AND #$10 : BNE + : RTL : +
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REP #$20 ; 16 A
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LDA.w #$08e1 ; square peg
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%writeTileAt(5,7,0,1)
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%writeTileAt(11,7,0,1)
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INC ;horizontal rail
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%writeTileAt(6,7,0,1)
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%writeTileAt(7,7,0,1)
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%writeTileAt(8,7,0,1)
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%writeTileAt(9,7,0,1)
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%writeTileAt(10,7,0,1)
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SEP #$20 ; 8 A
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REP #$20 ; 16 A
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LDA.w #$08e0 ; corner top left
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%writeTileAt(5,6,0,1)
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%writeTileAt(10,6,0,1)
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LDA.w #$48e0 ; corner top right
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%writeTileAt(6,6,0,1)
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%writeTileAt(11,6,0,1)
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LDA.w #$08f4 ; top mid
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%writeTileAt(7,6,0,1)
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%writeTileAt(8,6,0,1)
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%writeTileAt(9,6,0,1)
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LDA.w #$08f1 ; corner mid left
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%writeTileAt(5,7,0,1)
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%writeTileAt(10,7,0,1)
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LDA.w #$48f1 ; corner mid right
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%writeTileAt(6,7,0,1)
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%writeTileAt(11,7,0,1)
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LDA.w #$08f2 ; mid mid
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%writeTileAt(7,7,0,1)
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%writeTileAt(8,7,0,1)
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%writeTileAt(9,7,0,1)
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LDA.w #$08e4 ; corner lower left
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%writeTileAt(5,8,0,1)
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%writeTileAt(10,8,0,1)
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LDA.w #$48e4 ; corner lower right
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%writeTileAt(6,8,0,1)
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%writeTileAt(11,8,0,1)
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LDA.w #$08e5 ; lower mid
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%writeTileAt(7,8,0,1)
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%writeTileAt(8,8,0,1)
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%writeTileAt(9,8,0,1)
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SEP #$20 ; 8 A
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RTL
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;08e0 48e0 08f4 08f4 08e0 48e0
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;08f1 48f1 08f2 08f2 08f1 48f1
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;08e4 48e4 08e5 08e5 08e4 48e4
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;
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;(54,42) 22,10,1,1 42 85 2720 2742 156C
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;(54,43) 22,11,1,1 43 87 2784 2806 15EC
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;(54,44) 22,12,1,1 44 89 2848 2870 166C
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PoDArena:
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LDA.l DRFlags : AND #$10 : BNE + : RTL : +
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REP #$20 ; 16 A
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LDA.w #$08e0 ; corner top left
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%writeTileAt(22,10,1,1)
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%writeTileAt(25,10,1,1)
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LDA.w #$48e0 ; corner top right
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%writeTileAt(23,10,1,1)
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%writeTileAt(26,10,1,1)
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LDA.w #$08f4 ; top mid
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%writeTileAt(24,10,1,1)
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LDA.w #$08f1 ; corner mid left
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%writeTileAt(22,11,1,1)
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%writeTileAt(25,11,1,1)
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LDA.w #$48f1 ; corner mid right
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%writeTileAt(23,11,1,1)
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%writeTileAt(26,11,1,1)
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LDA.w #$08f2 ; mid mid
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%writeTileAt(24,11,1,1)
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LDA.w #$08e4 ; corner lower left
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%writeTileAt(22,12,1,1)
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%writeTileAt(25,12,1,1)
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LDA.w #$48e4 ; corner lower right
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%writeTileAt(23,12,1,1)
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%writeTileAt(26,12,1,1)
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LDA.w #$08e5 ; lower mid
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%writeTileAt(24,12,1,1)
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SEP #$20 ; 8 A
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RTL
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MireBKPond:
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LDA.l DRFlags : AND #$10 : BNE + : RTL : +
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REP #$20 ; 16 A
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LDA.w #$08e0 ; corner top left
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%writeTileAt(13,11,1,1)
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%writeTileAt(17,11,1,1)
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LDA.w #$48e0 ; corner top right
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%writeTileAt(14,11,1,1)
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%writeTileAt(18,11,1,1)
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LDA.w #$08f4 ; top mid
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%writeTileAt(15,11,1,1)
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%writeTileAt(16,11,1,1)
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LDA.w #$08f1 ; corner mid left
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%writeTileAt(13,12,1,1)
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%writeTileAt(17,12,1,1)
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LDA.w #$48f1 ; corner mid right
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%writeTileAt(14,12,1,1)
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%writeTileAt(18,12,1,1)
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LDA.w #$08f2 ; mid mid
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%writeTileAt(15,12,1,1)
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%writeTileAt(16,12,1,1)
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LDA.w #$08e4 ; corner lower left
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%writeTileAt(13,13,1,1)
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%writeTileAt(17,13,1,1)
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LDA.w #$48e4 ; corner lower right
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%writeTileAt(14,13,1,1)
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%writeTileAt(18,13,1,1)
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LDA.w #$08e5 ; lower mid
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%writeTileAt(15,13,1,1)
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%writeTileAt(16,13,1,1)
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SEP #$20 ; 8 A
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RTL
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RoomCallbackTable:
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; 0 1 2 3 4 5 6 7 8 9 A B C D E F
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $01, $00 ; 00x
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $06, $00, $00, $00, $00, $00 ; 01x
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $07, $00, $00, $00, $00, $00 ; 02x
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 01x
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 02x
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 03x
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 04x
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 05x
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@@ -234,7 +104,7 @@ RoomCallbackTable:
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Ax
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Bx
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Cx
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db $00, $08, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $03, $00 ; 0Dx
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $03, $00 ; 0Dx
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Ex
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Fx
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db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Fx
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