Initial, partially unsuccessful version

This commit is contained in:
Smallhacker
2018-01-03 23:33:45 -05:00
parent 0097425e1e
commit f97618da6a
5 changed files with 184 additions and 0 deletions

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@@ -123,6 +123,8 @@ incsrc compasses.asm
incsrc doorframefixes.asm
;incsrc shopkeeper.asm
incsrc cuccostorm.asm
incsrc roomloading.asm
incsrc graphicsoverride.asm
incsrc hashalphabet.asm ; <- TAKE OUT THE EXTRA ORGS IN HERE - THIS IS WHY WE COULDN'T ADD MORE FILES EARLIER
warnpc $A18000

62
graphicsoverride.asm Normal file
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macro OverwriteVramTile(firstTileIndex, count)
LDA.w #<firstTileIndex>+512*8*8*4/16
LDX.b #<count>
JSR UploadTileToVram
endmacro
GraphicsOverrideHook:
JSL .resumeOriginalCode
LDA $0A ; Floor tileset loaded
CMP #$0A ; Floor tileset index used by Ice and Mire
BEQ .loadedIceOrMireFloor
RTL
.loadedIceOrMireFloor
LDA $040C ; Load dungeon number
CMP #$12 ; Ice Palace
BEQ .isInIcePalace
RTL
.isInIcePalace
; We've just loading the floor tiles in Ice Palace.
; Replace the bridge tiles with the bombos medallion
LDA.b #IcePalaceMedallionGfx>>16
STA $02
REP #$20
LDA.w #IcePalaceMedallionGfx
STA $00
%OverwriteVramTile($CA, 2)
%OverwriteVramTile($DA, 2)
SEP #$20
RTL
.resumeOriginalCode
; Overwritten instructions:
PHB
LDA.b #$00
PHA
PLB
LDA.b #$80
JML GraphicsOverrideResume
; A = VRAM word address to upload to (Actual VRAM address / 2)
; X = Tiles to upload
; $00-$02 = Pointer to graphics data
UploadTileToVram:
; TODO: This should probably be optimized with a DMA
STA $2116
TXA : ASL #4 : TAX ; X = Amount of words to upload (Tiles to upload * 16)
- LDA [$00]
STA $2118
INC $00
INC $00
DEX
BNE -
RTS
IcePalaceMedallionGfx:
incbin ice_bombos_floor.bin

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@@ -1925,3 +1925,37 @@ org $0298AD ; <- Bank02.asm:4495 (LDA $010E : CMP.b #$43)
JSL.l WalkDownIntoTavern
NOP #1
;================================================================================
;================================================================================
; Hooks for roomloading.asm
;--------------------------------------------------------------------------------
org $02895D ; <- Bank02.asm:1812 (JSL Dungeon_LoadRoom)
JSL LoadRoomHook
;--------------------------------------------------------------------------------
org $028BE7 ; <- Bank02.asm:2299 (JSL Dungeon_LoadRoom)
JSL LoadRoomHook
;--------------------------------------------------------------------------------
org $029309 ; <- Bank02.asm:3533 (JSL Dungeon_LoadRoom)
JSL LoadRoomHook
;--------------------------------------------------------------------------------
org $02C2F3 ; <- Bank02.asm:10391 (JSL Dungeon_LoadRoom)
JSL LoadRoomHook
;================================================================================
;================================================================================
; Hook for graphicsoverride.asm
;--------------------------------------------------------------------------------
org $00E1DB ; <- Bank00.asm:4866 (PHB : PHK : PLB : LDA.b #$80)
JML GraphicsOverrideHook
NOP
GraphicsOverrideResume:
;--------------------------------------------------------------------------------
org $028BE7 ; <- Bank02.asm:2299 (JSL Dungeon_LoadRoom)
JSL LoadRoomHook
;--------------------------------------------------------------------------------
org $029309 ; <- Bank02.asm:3533 (JSL Dungeon_LoadRoom)
JSL LoadRoomHook
;--------------------------------------------------------------------------------
org $02C2F3 ; <- Bank02.asm:10391 (JSL Dungeon_LoadRoom)
JSL LoadRoomHook
;================================================================================

BIN
ice_bombos_floor.bin Normal file

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roomloading.asm Normal file
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LoadRoomHook:
JSL $01873A ; Dungeon_LoadRoom (Bank01.asm:726)
REP #$10 ; 16 bit XY
LDX $A0 ; Room ID
LDA RoomCallbackTable, X
SEP #$10 ; 8 bit XY
JSL $00879c ; UseImplicitRegIndexedLocalJumpTable
; Callback routines:
dl NoCallback ; 00
dl IcePalace1 ; 01
NoCallback:
RTL
!RL_TILE = 2
!RL_LINE = 128
macro setTilePointer(roomX, roomY, quadX, quadY)
; Left-to-right math. Should be equivalent to 0x7e2000+(roomX*2)+(roomY*128)+(quadX*64)+(quadY*4096)
LDX.w #<quadY>*32+<roomY>*2+<quadX>*32+<roomX>*2
endmacro
macro writeTile()
STA.l $7E2000,x
INX #2
endmacro
!IP_BORDER = #$08D0
!IP_ICON_1 = #$0CCA
!IP_ICON_2 = #$0CCB
!IP_ICON_3 = #$0CDA
!IP_ICON_4 = #$0CDB
!IP1_X = 14
!IP1_Y = 18
IcePalace1:
REP #$30 ; 16 AXY
%setTilePointer(!IP1_X, !IP1_Y, 1, 1)
LDA.w !IP_BORDER
%writeTile()
%writeTile()
%writeTile()
%writeTile()
%setTilePointer(!IP1_X, !IP1_Y+1, 1, 1)
%writeTile()
LDA.w !IP_ICON_1 : %writeTile()
LDA.w !IP_ICON_2 : %writeTile()
LDA.w !IP_BORDER : %writeTile()
%setTilePointer(!IP1_X, !IP1_Y+2, 1, 1)
%writeTile()
LDA.w !IP_ICON_3 : %writeTile()
LDA.w !IP_ICON_4 : %writeTile()
LDA.w !IP_BORDER : %writeTile()
%setTilePointer(!IP1_X, !IP1_Y+3, 1, 1)
%writeTile()
%writeTile()
%writeTile()
%writeTile()
SEP #$30 ; 8 AXY
RTL
RoomCallbackTable:
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $01, $00 ; 00x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 01x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 02x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 03x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 04x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 05x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 06x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 07x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 08x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 09x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Ax
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Bx
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Cx
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Dx
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Ex
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Fx
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 0Fx
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 10x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 11x
db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 ; 12x